View ML610Q419_8192318.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fedl610q419-05 issue date: july, 25, 2014 ML610Q419/ML610Q419c 8-bit microcontroller with a built-in lcd driver 1/38 general description this lsi is a high-performance 8-bit cmos microcontroller into which rich peripheral circuits, such as synchronous serial port, uart, i2c bus interface (master), melody driver, battery level detect circuit, rc oscillation type a/d converter, and lcd driver, are incorporated around 8-bit cpu nx-u8/100. the cpu nx-u8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel procesing. the flash rom that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask rom and is most suitable for battery-driven applications. the on-chip debug function that is installed enables program debugging and programming. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function ? minimum instruction execution time 30.5 s (@32.768 khz system clock) 0.24 4 s (@4.096 mhz system clock) ? internal memory ? internal 64kbyte flash rom (32k 16 bits) (including unusable 1kbyte test area) ? internal 4kbyte data flash (2k 16 bits) ? internal 2kbyte data ram (2048 8 bits), 240 9bit display allocation ram ? interrupt controller ? 1 non-maskable interrupt sources (internal source: 1) ? 21 maskable interrupt sources (internal sources: 16, external sources: 5) ? time base counter ? low-speed time base counter 1 channel frequency compensation (compensation range: approx. ? 488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) ? high-speed time base counter 1 channel ? watchdog timer ? non-maskable interrupt and reset ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) ? timers ? 8 bits 4 channels (timer0-3: 16-bit x 2 configuration available by using timer0-1 or timer2-3) ? clock frequency measurement mode (in one channel of 16-bit configuration using timer2-3)
fedl610q419-05 ML610Q419/ML610Q419c 2/38 ? capture ? time base capture 2 channels (4096 hz to 32 hz) ? pwm ? resolution 16 bits 1 channel ? synchronous serial port ? master/slave selectable 2 channel ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? txd/rxd 1 channel ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? i 2 c bus interface ? master function only ? fast mode (400 kbps@ mh ), standard mode (100 kbps@1mh , 50kbps@500khz) ? melody driver ? scale: 29 types (melody sound frequency: 508 hz to 32.768 khz) ? tone length: 63 types ? tempo: 15 types ? buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) ? rc oscillation type a/d converter ? 24-bit counter ? time division 2 channels ? successive approximation type a/d converter (sa-adc) ? 12-bit a/d converter ? input 4 channels ? general-purpose ports ? input-only port 6 channels (including secondary functions) ? output-only port 3 channels (including secondary functions) ? input/output port ML610Q419 : 18 channels (including secondary functions) ML610Q419c : 26 channels (including secondary functions)
fedl610q419-05 ML610Q419/ML610Q419c 3/38 ? lcd driver ? dot matrix can be supported. ML610Q419 : 192 dots max. (48 seg 4 com) ML610Q419c : 160 dots max. (40 seg 4 com) ? 1/1 to 1/4 duty ? 1/2, 1/3 bias (built-in bias generation circuit) ? frame frequency selecable: approx. 64hz, 73hz, 85hz, and 102hz ? bias voltage multiplying clock selectable (8 types) ? lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? programmable display allocation function ? reset ? reset by the reset_n pin ? reset by power-on detection ? reset when oscillation stop of the low-speed clock is detected ? reset by low level detection (lld) the voltage which is released from reset is selectable by the code-option: 1.1v, 1.8v (max.) ? reset by the watchdog timer (wdt) 2 nd overflow ? power supply voltage detect function ? judgment voltages: one of 16 levels ? judgment accuracy: 2% (typ.) ? clock ? low-speed clock: (this lsi can not guarantee the operation withoug low-speed clock) crystal oscillation (32.768 khz) ? high-speed clock: built-in rc oscillation (500khz) built-in pll oscillation (8.192 mhz 2.5%), crystal/ceramic oscillation (4.096 mhz), external clock ? selection of high-speed clock mode by software: built-in rc oscillation, built-in pll oscillation, crystal/ceramic oscillation, external clock ? power management ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals. ? guaranteed operating range ? operating temperature: ? 20 c to 70 c (p version: ? 40 c to 85 c) ? operating voltage: v dd = 1.1v to 3.6v
fedl610q419-05 ML610Q419/ML610Q419c 4/38 ? product name ? s upported function - chip (die) - rom type operating temperature lcd driver product availability ML610Q419- xxxwa flash rom -20c to +70c 192 dots max. (48 seg x 4 com) yes ML610Q419p-xxxwa flash rom -40c to +85c 192 dots max. (48 seg x 4 com) yes ML610Q419c -xxxwa flash rom -20c to +70c 160 dots max. (40 seg x 4 com) yes ML610Q419pc - xxxwa flash rom -40c to +85c 160 dots max. (40 seg x 4 com) yes -100-pin plastic tqfp - rom type operating temperature lcd driver product availability ML610Q419- xxxtb flash rom -20c to +70c 192 dots max. (48 seg x 4 com) yes ML610Q419p-xxxtb flash rom -40c to +85c 192 dots max. (48 seg x 4 com) yes ML610Q419c -xxxtb flash rom -20c to +70c 160 dots max. (40 seg x 4 com) yes ML610Q419pc - xxxtb flash rom -40c to +85c 160 dots max. (40 seg x 4 com) yes xxx: rom code number (xxx of the blank product is nnn) q:flash rom version p: wide range temperature version wa: chip tb: tqfp
fedl610q419-05 ML610Q419/ML610Q419c 5/38 block diagram ML610Q419 block diagram figure 1 show the block diagram of the ML610Q419. "*" indicates the secondary function of each port. figure 1 ML610Q419 block diagram program memory (flash) 64kbyte + data flash 4kbyte ssio 2 sck0* sin0* sout0* uart rxd0* txd0* i 2 c sda* scl* int 2 ram 2048byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 int 1 int 1 wdt int 4 8bit timer 2 int 1 pwm gpio p10 to p11 p20 to p22 int 5 p30 to p35 p40 to p47 data-bus pwm0* melody int 1 md0* test0 reset_n osc xt0 xt1 osc0* osc1* lsclk* outclk* bld power v ddl lcd driver com0 to com3 seg0 to seg47 lcd bias v l1 , v l2 , v l3 c1, c2 rc-adc 2 cs0* in0* rs0* rt0* crt0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss int 1 display register 192bit display allocation ram p00 to p03 test1_n p50 to p53 av dd av ss 12bit-adc ain0, ain1, ain2, ain3 v ref int 1 sck1* sin1* sout1* capture 2
fedl610q419-05 ML610Q419/ML610Q419c 6/38 ML610Q419c block diagram figure 2 show the block diagram of the ML610Q419c. "*" indicates the secondary function of each port. figure 2 ML610Q419c block diagram program memory (flash) 64kbyte + data flash 4kbyte ssio 2 sck0* sin0* sout0* uart rxd0* txd0* i 2 c sda* scl* int 2 ram 2048byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 int 1 int 1 wdt int 4 8bit timer 2 int 1 pwm gpio p10 to p11 p20 to p22 int 5 p30 to p35 p40 to p47 data-bus pwm0* melody int 1 md0* test0 reset_n osc xt0 xt1 osc0* osc1* lsclk* outclk* bld power v ddl lcd driver com0 to com3 seg0 to seg39 lcd bias v l1 , v l2 , v l3 c1, c2 rc-adc 2 cs0* in0* rs0* rt0* crt0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss int 1 display register 192bit display allocation ram p00 to p03 test1_n p50 to p53 av dd av ss 12bit-adc ain0, ain1, ain2, ain3 v ref int 1 sck1* sin1* sout1* capture 2 p60 to p67
fedl610q419-05 ML610Q419/ML610Q419c 7/38 pin configuration ML610Q419 tqfp100 pin layout v ref reset_n test1_n av ss v ss p20 p21 p22 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl xt0 xt1 test0 v l1 v l2 v l3 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 (nc): no connection figure 3 ML610Q419 tqfp100 pin configuration
fedl610q419-05 ML610Q419/ML610Q419c 8/38 ML610Q419c tqfp100 pin layout (nc): no connection figure 4 ML610Q419c tqfp100 pin configuration
fedl610q419-05 ML610Q419/ML610Q419c 9/38 ML610Q419 chip dimension chip size: 2.64 mm 3.20 mm pad count: 100 pins minimum pad pitch: 80 m pad aperture: 70 m 70 m chip thickness: 350 m voltage of the rear side of chip: v ss level figure 5 ML610Q419 chip dimension
fedl610q419-05 ML610Q419/ML610Q419c 10/38 ML610Q419c chip dimension v ref 1 av ss 2 v ss 3 p20 4 p21 5 p22 6 p40 7 p41 8 p42 9 p43 10 p44 11 p45 12 p46 13 p47 14 v dd 15 v ss 16 v ddl 17 xt0 18 xt1 19 reset_n 20 21 22 v l1 23 v l2 24 v l3 25 seg18 50 seg19 51 seg20 52 seg21 53 seg22 54 seg23 55 seg24 56 test0 test1_n seg25 57 seg26 58 seg27 59 seg28 60 seg29 61 seg30 62 seg31 63 seg32 64 seg33 65 seg34 66 seg35 67 seg36 68 seg37 69 seg38 70 seg39 71 p60 72 p61 73 p62 74 p63 75 chip size: 2.64 mm 3.20 mm pad count: 100 pins minimum pad pitch: 80 m pad aperture: 70 m 70 m chip thickness: 350 m voltage of the rear side of chip: v ss level figure 6 ML610Q419c chip dimension
fedl610q419-05 ML610Q419/ML610Q419c 11/38 ML610Q419 pad coordinates table 1 ML610Q419 pad coordinates chip center: x=0,y=0 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 v ref -1020.0 -1494.0 36 seg4 1214.0 -525.0 71 seg39 -620.0 1494.0 2 av ss -860.0 -1494.0 37 seg5 1214.0 -445.0 72 seg40 -730.0 1494.0 3 v ss -780.0 -1494.0 38 seg6 1214.0 -365.0 73 seg41 -810.0 1494.0 4 p20 -700.0 -1494.0 39 seg7 1214.0 -285.0 74 seg42 -890.0 1494.0 5 p21 -620.0 -1494.0 40 seg8 1214.0 -205.0 75 seg43 -970.0 1494.0 6 p22 -540.0 -1494.0 41 seg9 1214.0 52.0 76 seg44 -1214.0 1380.0 7 p40 -460.0 -1494.0 42 seg10 1214.0 258.0 77 seg45 -1214.0 1300.0 8 p41 -380.0 -1494.0 43 seg11 1214.0 464.0 78 seg46 -1214.0 1220.0 9 p42 -280.0 -1494.0 44 seg12 1214.0 670.0 79 seg47 -1214.0 1140.0 10 p43 -200.0 -1494.0 45 seg13 1214.0 876.0 80 p01 -1214.0 1040.0 11 p44 -120.0 -1494.0 46 seg14 1214.0 1015.0 81 p00 -1214.0 850.0 12 p45 -40.0 -1494.0 47 seg15 1214.0 1095.0 82 p11 -1214.0 760.0 13 p46 40.0 -1494.0 48 seg16 1214.0 1175.0 83 p10 -1214.0 600.0 14 p47 120.0 -1494.0 49 seg17 1214.0 1255.0 84 p50 -1214.0 476.0 15 v dd 204.0 -1494.0 50 seg18 1060.0 1494.0 85 p51 -1214.0 270.0 16 v ss 284.0 -1494.0 51 seg19 980.0 1494.0 86 p52 -1214.0 28.0 17 v ddl 364.0 -1494.0 52 seg20 900.0 1494.0 87 p53 -1214.0 -52.0 18 xt0 452.0 -1494.0 53 seg21 820.0 1494.0 88 p02 -1214.0 -132.0 19 xt1 612.0 -1494.0 54 seg22 740.0 1494.0 89 p03 -1214.0 -212.0 20 reset_n 692.0 -1494.0 55 seg23 660.0 1494.0 90 p30 -1214.0 -292.0 21 test0 772.0 -1494.0 56 seg24 580.0 1494.0 91 p31 -1214.0 -372.0 22 test1_n 852.0 -1494.0 57 seg25 500.0 1494.0 92 p34 -1214.0 -452.0 23 v l1 932.0 -1494.0 58 seg26 420.0 1494.0 93 p32 -1214.0 -532.0 24 v l2 1012.0 -1494.0 59 seg27 340.0 1494.0 94 p33 -1214.0 -612.0 25 v l3 1092.0 -1494.0 60 seg28 260.0 1494.0 95 p35 -1214.0 -692.0 26 c1 1214.0 -1325.0 61 seg29 180.0 1494.0 96 ain0 -1214.0 -833.0 27 c2 1214.0 -1245.0 62 seg30 100.0 1494.0 97 ain1 -1214.0 -913.0 28 com0 1214.0 -1165.0 63 seg31 20.0 1494.0 98 ain02 -1214.0 -1085.0 29 com1 1214.0 -1085.0 64 seg32 -60.0 1494.0 99 ain03 -1214.0 -1165.0 30 com2 1214.0 -1005.0 65 seg33 -140.0 1494.0 100 av dd -1214.0 -1291.0 31 com3 1214.0 -925.0 66 seg34 -220.0 1494.0 32 seg0 1214.0 -845.0 67 seg35 -300.0 1494.0 33 seg1 1214.0 -765.0 68 seg36 -380.0 1494.0 34 seg2 1214.0 -685.0 69 seg37 -460.0 1494.0 35 seg3 1214.0 -605.0 70 seg38 -540.0 1494.0
fedl610q419-05 ML610Q419/ML610Q419c 12/38 ML610Q419c pad coordinates table 2 ML610Q419c pad coordinates chip center: x=0,y=0 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 v ref -1020.0 -1494.0 36 seg4 1214.0 -525.0 71 seg39 -620.0 1494.0 2 av ss -860.0 -1494.0 37 seg5 1214.0 -445.0 72 p60 -730.0 1494.0 3 v ss -780.0 -1494.0 38 seg6 1214.0 -365.0 73 p61 -810.0 1494.0 4 p20 -700.0 -1494.0 39 seg7 1214.0 -285.0 74 p62 -890.0 1494.0 5 p21 -620.0 -1494.0 40 seg8 1214.0 -205.0 75 p63 -970.0 1494.0 6 p22 -540.0 -1494.0 41 seg9 1214.0 52.0 76 p64 -1214.0 1380.0 7 p40 -460.0 -1494.0 42 seg10 1214.0 258.0 77 p65 -1214.0 1300.0 8 p41 -380.0 -1494.0 43 seg11 1214.0 464.0 78 p66 -1214.0 1220.0 9 p42 -280.0 -1494.0 44 seg12 1214.0 670.0 79 p67 -1214.0 1140.0 10 p43 -200.0 -1494.0 45 seg13 1214.0 876.0 80 p01 -1214.0 1040.0 11 p44 -120.0 -1494.0 46 seg14 1214.0 1015.0 81 p00 -1214.0 850.0 12 p45 -40.0 -1494.0 47 seg15 1214.0 1095.0 82 p11 -1214.0 760.0 13 p46 40.0 -1494.0 48 seg16 1214.0 1175.0 83 p10 -1214.0 600.0 14 p47 120.0 -1494.0 49 seg17 1214.0 1255.0 84 p50 -1214.0 476.0 15 v dd 204.0 -1494.0 50 seg18 1060.0 1494.0 85 p51 -1214.0 270.0 16 v ss 284.0 -1494.0 51 seg19 980.0 1494.0 86 p52 -1214.0 28.0 17 v ddl 364.0 -1494.0 52 seg20 900.0 1494.0 87 p53 -1214.0 -52.0 18 xt0 452.0 -1494.0 53 seg21 820.0 1494.0 88 p02 -1214.0 -132.0 19 xt1 612.0 -1494.0 54 seg22 740.0 1494.0 89 p03 -1214.0 -212.0 20 reset_n 692.0 -1494.0 55 seg23 660.0 1494.0 90 p30 -1214.0 -292.0 21 test0 772.0 -1494.0 56 seg24 580.0 1494.0 91 p31 -1214.0 -372.0 22 test1_n 852.0 -1494.0 57 seg25 500.0 1494.0 92 p34 -1214.0 -452.0 23 v l1 932.0 -1494.0 58 seg26 420.0 1494.0 93 p32 -1214.0 -532.0 24 v l2 1012.0 -1494.0 59 seg27 340.0 1494.0 94 p33 -1214.0 -612.0 25 v l3 1092.0 -1494.0 60 seg28 260.0 1494.0 95 p35 -1214.0 -692.0 26 c1 1214.0 -1325.0 61 seg29 180.0 1494.0 96 ain0 -1214.0 -833.0 27 c2 1214.0 -1245.0 62 seg30 100.0 1494.0 97 ain1 -1214.0 -913.0 28 com0 1214.0 -1165.0 63 seg31 20.0 1494.0 98 ain02 -1214.0 -1085.0 29 com1 1214.0 -1085.0 64 seg32 -60.0 1494.0 99 ain03 -1214.0 -1165.0 30 com2 1214.0 -1005.0 65 seg33 -140.0 1494.0 100 av dd -1214.0 -1291.0 31 com3 1214.0 -925.0 66 seg34 -220.0 1494.0 32 seg0 1214.0 -845.0 67 seg35 -300.0 1494.0 33 seg1 1214.0 -765.0 68 seg36 -380.0 1494.0 34 seg2 1214.0 -685.0 69 seg37 -460.0 1494.0 35 seg3 1214.0 -605.0 70 seg38 -540.0 1494.0
fedl610q419-05 ML610Q419/ML610Q419c 13/38 pin list pad no. primary function secondary function tertiary function q419 q419c pin name i/o function pin name i/o function pin name i/o function 3, 16 3. 16 vss ? negative power supply pin ? ? ? ? ? ? 15 15 v dd ? positive power supply pin ? ? ? ? ? ? 17 17 v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? ? ? 2 2 av ss ? negative power supply pin for successive approximation type adc ? ? ? ? ? ? 100 100 av dd ? positive power supply pin for successive approximation type adc ? ? ? ? ? ? 1 1 v ref ? reference power supply pin for successive approximation type adc ? ? ? ? ? ? 96 96 ain0 ? successive approximation type adc input ? ? ? ? ? ? 97 97 ain1 ? successive approximation type adc input ? ? ? ? ? ? 98 98 ain2 ? successive approximation type adc input ? ? ? ? ? ? 99 99 ain3 ? successive approximation type adc input ? ? ? ? ? ? 23 23 v l1 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 24 24 v l2 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 25 25 v l3 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 26 26 c1 ? capacitor connection pin for lcd bias generation ? ? ? ? ? ? 27 27 c2 ? capacitor connection pin for lcd bias generation ? ? ? ? ? ? 21 21 test0 i/o test pin ? ? ? ? ? ? 22 22 test1_n i test pin ? ? ? ? ? ? 20 20 reset_n i reset input pin ? ? ? ? ? ? 18 18 xt0 i low-speed clock oscillation pin ? ? ? ? ? ? 19 19 xt1 o low-speed clock oscillation pin ? ? ? ? ? ? 81 81 p00/exi0/ cap0 i input port, external interrupt, capture 0 input ? ? ? ? ? ? 80 80 p01/exi1/ cap1 i input port, external interrupt, capture 1 input ? ? ? ? ? ? 88 88 p02/exi2 /rxd0 i input port, external interrupt, uart0 received data ? ? ? ? ? ?
fedl610q419-05 ML610Q419/ML610Q419c 14/38 pad no. primary function secondary function tertiary function q419 q419c pin name i/o function pin name i/o function pin name i/o function 89 89 p03/exi3 i input port, external interrupt ? ? ? ? ? ? 83 83 p10 i input port osc0 i high-speed oscillation ? ? ? 82 82 p11 i input port osc1 o high-speed oscillation ? ? ? 4 4 p20/led0 o output port lsclk o low-speed clock output ? ? ? 5 5 p21/led 1 o output port outclk o high-speed clock output ? ? ? 6 6 p22/led 2 o output port md0 o melody 0 output ? ? ? 90 90 p30 i/o input/output port in0 i rc type adc0 oscillation input pin ? ? ? 91 91 p31 i/o input/output port cs0 o rc type adc0 reference capacitor connection pin ? ? ? 93 93 p32 i/o input/output port rs0 o rc type adc0 reference resistor connection pin ? ? ? 94 94 p33 i/o input/output port rt0 o rc type adc0 measurement resistor sensor connection pin ? ? ? 92 92 p34 i/o input/output port rct0 o rc type adc0 resistor/capacitor sensor connection pin pwm0 o pwm output 95 95 p35 i/o input/output port rcm o rc type adc oscillation monitor ? ? ? 7 7 p40 i/o input/output port sda i/o i2c data input/output sin0 i ssio0 data input 8 8 p41 i/o input/output port scl i/o i2c clock input/output sck0 i/o ssio0 synchronous clock 9 9 p42 i/o input/output port rxd0 i uart data input sout0 o ssio0 data output 10 10 p43 i/o input/output port txd0 o uart data output pwm0 o pwm output 11 11 p44/t02p 0ck i/o input/output port, timer 0/timer 2/pwm0 external clock input in1 i rc type adc1 oscillation input pin sin0 i ssio0 data input 12 12 p45/t13c k i/o input/output port, timer 1/timer 3 external clock input cs1 o rc type adc1 reference capacitor connection pin sck0 i/o ssio0 synchronous clock 13 13 p46 i/o input/output port rs1 o rc type adc1 reference resistor connection pin sout0 o ssio0 data output 14 14 p47 i/o input/output port rt1 o rc type adc1 resistor sensor connection pin ? ? ? 84 84 p50/exi8 i/o input/output port, external interrupt md0 o melody 0 output sin1 i ssio1 data input 85 85 p51/exi8 i/o input/output port, external interrupt ? ? ? sck1 i/o ssio1 synchronous clock input/output 86 86 p52/exi8 i/o input/output port, external interrupt ? ? ? sout1 o ssio1 data output 87 87 p53/exi8 i/o input/output port, external interrupt ? ? ? ? ? ? 28 28 com0 o lcd common pin ? ? ? ? ? ? 29 29 com1 o lcd common pin ? ? ? ? ? ? 30 30 com2 o lcd common pin ? ? ? ? ? ? 31 31 com3 o lcd common pin ? ? ? ? ? ?
fedl610q419-05 ML610Q419/ML610Q419c 15/38 pad no. primary function secondary function tertiary function q419 q419c pin name i/o function pin name i/o function pin name i/o function 32 32 seg0 o lcd segment pin ? ? ? ? ? ? 33 33 seg1 o lcd segment pin ? ? ? ? ? ? 34 34 seg2 o lcd segment pin ? ? ? ? ? ? 35 35 seg3 o lcd segment pin ? ? ? ? ? ? 36 36 seg4 o lcd segment pin ? ? ? ? ? ? 37 37 seg5 o lcd segment pin ? ? ? ? ? ? 38 38 seg6 o lcd segment pin ? ? ? ? ? ? 39 39 seg7 o lcd segment pin ? ? ? ? ? ? 40 40 seg8 o lcd segment pin ? ? ? ? ? ? 41 41 seg9 o lcd segment pin ? ? ? ? ? ? 42 42 seg10 o lcd segment pin ? ? ? ? ? ? 43 43 seg11 o lcd segment pin ? ? ? ? ? ? 44 44 seg12 o lcd segment pin ? ? ? ? ? ? 45 45 seg13 o lcd segment pin ? ? ? ? ? ? 46 46 seg14 o lcd segment pin ? ? ? ? ? ? 47 47 seg15 o lcd segment pin ? ? ? ? ? ? 48 48 seg16 o lcd segment pin ? ? ? ? ? ? 49 49 seg17 o lcd segment pin ? ? ? ? ? ? 50 50 seg18 o lcd segment pin ? ? ? ? ? ? 51 51 seg19 o lcd segment pin ? ? ? ? ? ? 52 52 seg20 o lcd segment pin ? ? ? ? ? ? 53 53 seg21 o lcd segment pin ? ? ? ? ? ? 54 54 seg22 o lcd segment pin ? ? ? ? ? ? 55 55 seg23 o lcd segment pin ? ? ? ? ? ? 56 56 seg24 o lcd segment pin ? ? ? ? ? ? 57 57 seg25 o lcd segment pin ? ? ? ? ? ? 58 58 seg26 o lcd segment pin ? ? ? ? ? ? 59 59 seg27 o lcd segment pin ? ? ? ? ? ? 60 60 seg28 o lcd segment pin ? ? ? ? ? ? 61 61 seg29 o lcd segment pin ? ? ? ? ? ? 62 62 seg30 o lcd segment pin ? ? ? ? ? ? 63 63 seg31 o lcd segment pin ? ? ? ? ? ? 64 64 seg32 o lcd segment pin ? ? ? ? ? ? 65 65 seg33 o lcd segment pin ? ? ? ? ? ? 66 66 seg34 o lcd segment pin ? ? ? ? ? ? 67 67 seg35 o lcd segment pin ? ? ? ? ? ? 68 68 seg36 o lcd segment pin ? ? ? ? ? ? 69 69 seg37 o lcd segment pin ? ? ? ? ? ? 70 70 seg38 o lcd segment pin ? ? ? ? ? ? 71 71 seg39 o lcd segment pin ? ? ? ? ? ? 72 ? seg40 o lcd segment pin ? ? ? ? ? ? 73 ? seg41 o lcd segment pin ? ? ? ? ? ? 74 ? seg42 o lcd segment pin ? ? ? ? ? ? 75 ? seg43 o lcd segment pin ? ? ? ? ? ? 76 ? seg44 o lcd segment pin ? ? ? ? ? ? 77 ? seg45 o lcd segment pin ? ? ? ? ? ? 78 ? seg46 o lcd segment pin ? ? ? ? ? ? 79 ? seg47 o lcd segment pin ? ? ? ? ? ? ? 72 p60 i/o input/output port ? ? ? ? ? ? ? 73 p61 i/o input/output port ? ? ? ? ? ? ? 74 p62 i/o input/output port ? ? ? ? ? ? ? 75 p63 i/o input/output port ? ? ? ? ? ? ? 76 p64 i/o input/output port ? ? ? ? ? ?
fedl610q419-05 ML610Q419/ML610Q419c 16/38 pad no. primary function secondary function tertiary function q419 q419c pin name i/o function pin name i/o function pin name i/o function ? 77 p65 i/o input/output port ? ? ? ? ? ? ? 78 p66 i/o input/output port ? ? ? ? ? ? ? 79 p67 i/o input/output port ? ? ? ? ? ?
fedl610q419-05 ML610Q419/ML610Q419c 17/38 pin description pin name i/o description primary/ secondary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal oscillator (see measuring circuit 1) is connected to this pin. capacitors cdl and cgl are connected across this pin and v ss as required. ? ? osc0 i secondary ? osc1 o crystal/ceramic connection pin for high-speed clock. a crystal or ceramic is connected to this pin (4.1 mhz max.). capacitors cdh and cgh (see measuring circuit 1) are connected across this pin and v ss . this pin is used as the secondary function of the p10 pin(osc0) and p11 pin(osc1). secondary ? lsclk o low-speed clock output pin. this pin is used as the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00-p03 i general-purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p10-p11 i general-purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose output port p20-p22 o general-purpose output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose input/output port p30-p35 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p40-p47 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p50-p53 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p60-p67 i/o general-purpose input/output port. these pins are for the ML610Q419c, but are not provided in the ML610Q419. primary positive
fedl610q419-05 ML610Q419/ML610Q419c 18/38 pin name i/o description primary/ secondary/ tertiary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary/se condary positive i 2 c bus interface sda i/o i 2 c data input/output pin. this pin is used as the secondary function of the p40 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive scl o i 2 c clock output pin. this pin is used as the secondary function of the p41 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive synchronous serial (ssio) sck0 i/o synchronous serial clock input/output pin. this pin is used as the tertiary function of the p41 or p45 pin. tertiary ? sin0 i synchronous serial data input pin. this pin is used as the tertiary function of the p40 or p44 pin. tertiary positive sout0 o synchronous serial data output pin. this pin is used as the tertiary function of the p42 or p46 pin. tertiary positive sck1 i/o synchronous serial clock input/output pin. this pin is used as the tertiary function of the p51 pin. tertiary ? sin1 i synchronous serial data input pin. this pin is used as the tertiary function of the p50 pin. tertiary positive sout1 o synchronous serial data output pin. this pin is used as the tertiary function of the p52 pin. tertiary positive pwm pwm0 o pwm0 output pin. this pin is used as the tertiary function of the p43 or p34 pin. tertiary positive t0p0ck i pwm0 external clock input pin. this pin is used as the primary function of the p44 pin. primary ? external interrupt exi0-3 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00-p03 pins. primary positive/ negative exi8 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p50-p53 pins. primary positive/ negative capture cap0 i primary ? cap1 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary ? timer t0p0ck i external clock input pin used for timer 0. this pin is used as the primary function of the p44 pin. primary ? t1p1ck i external clock input pin used for timer 1. this pin is used as the primary function of the p45 pin. primary ? melody md0 o melody/buzzer signal output pin. this pin is used as the secondary function of the p22 pin. secondary positive/ negative led drive led0-2 o nch open drain output pins to drive led. primary positive/ negative
fedl610q419-05 ML610Q419/ML610Q419c 19/38 pin name i/o description primary/ secondary/ tertiary logic rc oscillation type a/d converter in0 i channel 0 oscillation input pin. this pin is used as the secondary function of the p30 pin. secondary ? cs0 o channel 0 reference capacitor connection pin. this pin is used as the secondary function of the p31 pin. secondary ? rs0 o this pin is used as the secondary function of the p32 pin which is the reference resistor connection pin of channel 0. secondary ? rt0 o resistor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p34 pin. secondary ? crt0 o resistor/capacitor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p33 pin. secondary ? rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1. this pin is used as the secondary function of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ? successive approximation type a/d converter av ss ? negative power supply pin for successive approximation type a/d converter. ? ? av dd ? positive power supply pin for successive approximation type a/d converter. ? ? v ref ? reference power supply pin for successive approximation type a/d converter. ? ? ain0 i channel 0 analog input for successive approximation type a/d converter. ? ? ain1 i channel 1 analog input for successive approximation type a/d converter. ? ? ain2 i channel 2 analog input for successive approximation type a/d converter. ? ? ain3 i channel 3 analog input for successive approximation type a/d converter. ? ? lcd drive signal com0-3 o common output pins. ? ? seg0-39 o segment output pins. ? ? seg40-47 o segment output pins. these pins are for the ML610Q419, but are not provided in the ML610Q419c. ? ? lcd driver power supply v l1 ? ? ? v l2 ? ? ? v l3 ? power supply pins for lcd bias (internally generated). capacitors ca, cb, and cc (see measuring circuit 1) are connected between v ss and v l1 , v l2 , and v l3 respectively. ? ? c1 ? ? ? c2 ? power supply pins for lcd bias (internally generated). capacitors c12 is connected between c1 and c2. ? ? for testing test0 i/o input/output pin for testing. a pull-down resistor is internally connected. ? ? test1_n i input/output pin for testing. a pull-up resistor is internally connected. ? ? power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitors cl0 and cl1 (see measuring circuit 1) are connected between this pin and v ss . ? ?
fedl610q419-05 ML610Q419/ML610Q419c 20/38 termination of unused pins table 3 shows methods of terminating the unused pins. table 3 termination of unused pins pin recommended pin termination av dd v ss av ss v ss v ref v ss ain0, ain1, ain2, ain3 open v l1 , v l2 , v l3 open c1, c2 open reset_n open test0 open test1_n open p00 to p03 v dd or v ss p10 to p11 v dd p20 to p22 open p30 to p35 open p40 to p47 open p50 to p53 open p60 to p67 open com0 to 3 open seg0 to 47 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. the main difference points of ML610Q419 and ML610Q419c table 4 the main difference points of ML610Q419 and ML610Q419c function ML610Q419 ML610Q419c lcd seg seg47 to seg0 seg39 to seg0
fedl610q419-05 ML610Q419/ML610Q419c 21/38 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 c ? 0.3 to +4.6 v power supply voltage 2 av dd ta = 25 c ? 0.3 to +4.6 v power supply voltage 3 v ddl ta = 25 c ? 0.3 to +3.6 v power supply voltage 4 v l1 ta = 25 c ? 0.3 to +1.75 v power supply voltage 5 v l2 ta = 25 c ? 0.3 to +3.5 v power supply voltage 6 v l3 ta = 25 c ? 0.3 to +5.25 v input voltage v in ta = 25 c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 c ? 0.3 to v dd +0.3 v output current 1 i out1 port3?5, ta = 25 c ? 12 to +11 ma output current 2 i out2 port2, ta = 25 c ? 12 to +20 ma power dissipation pd ta = 25 c 0.9 w storage temperature t stg ? ? 55 to +150 c recommended operat ing conditions (v ss = 0v) parameter symbol condition range unit non - p version -20 +70 c operating temperature t op p version -40 +85 c f op = 30k to 625khz 1.1 3.6 v operating voltage v dd f op = 30k to 4.2mhz 1.8 3.6 v vdd = 1.1 3.6v 30k 36k vdd = 1.3 3.6v 30k 650k operating frequency (cpu) f op vdd = 1.8 3.6v 30k 4.2m hz capacitor externally connected to v dd pin c v ? more than 2.2 30% f c l0 ? 2.2 30% capacitor externally connected to v ddl pin c l1 ? 0.1 30% f capacitors externally connected to v l1, 2, 3 pins c a b c ? 0.1 30% f capacitors externally connected across c1 and c2 pins c 12 ? 0.47 30% f
fedl610q419-05 ML610Q419/ML610Q419c 22/38 clock generation circuit operating conditions (v ss = 0v) rating parameter symbol condition min. typ. max. unit low-speed crystal oscillation frequency f xtl ? ? 32.768k ? hz recommended equivalent series resistance value of low-speed crystal oscillation r l ? ? ? 40k ? c l =6pf of crystal oscillation *2 ? 3 ? c l =9pf of crystal oscillation ? 9 ? low-speed crystal oscillation external capacitor *1 c dl /c gl c l =12pf of crystal oscillation ? 15 ? pf high-speed crystal/ceramic oscillation frequency f xth ? ? 4.0m / 4.096m ? hz c dh ? ? 24 ? high-speed crystal oscillation external capacitor c gh ? ? 24 ? pf *1 : the external c dl and c gl need to be adjusted in consideration of variation of internal loading capacitance c d and c g , and other additional capacitance such as pcb layout. *2 : when using a crystal oscillator c l = 6pf, there is a possibility that can not be adjusted by external c dl and c gl . operating conditions of flash rom (v ss = 0v) rating parameter symbol condition min. typ. max. unit flash rom, at write/erase 0 ? +40 c operating temperature t op data flash memory, at write/erase -40 ? +85 c operating voltage v dd at write/erase 1.8 ? 3.6 v flash rom ? ? 100 rewrite counts c ep data flash memory ? ? 10k cycles flash rom 10 ? data retention y dr data flash memory, 1000 cycles 10 ? years chip-erase time t cerase ? 85 100 ms block-erase time t berase ? 85 100 ms sector-erase time t serase ? 85 100 ms 1-word (16 bits) write time t write ? 18 40 s
fedl610q419-05 ML610Q419/ML610Q419c 23/38 dc characteristics (1/5) (v dd = 1.1 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta = 25 c typ. ? 10% 500 typ. + 10% khz 500khz rc oscillation frequency f rc v dd = 1.3 to 3.6v * 5 typ. ? 25% 500 typ. + 25% khz pll oscillation frequency* 4 f pll lsclk = 32.768khz v dd = 1.8 to 3.6v -2.5% 8.192 +2.5% mhz low-speed crystal oscillation start time* 2 t xtl ? ? 0.3 2 s 500khz rc oscillation start time t rc ? ? 50 500 s high-speed crystal oscillation start time* 3 t xth v dd = 1.8 to 3.6v D 2 20 pll oscillation start time t pll v dd = 1.8 to 3.6v D 1 10 low-speed oscillation stop detect time *1 t stop ? 0.2 3 20 ms reset pulse width p rst ? 200 ? ? reset noise elimination pulse width p nrst ? ? ? 0.3 s power-on reset activation power rise time t por ? ? ? 10 ms cold0=0* 6 ? ? 1.1 low level reset detection voltage v llr cold0=1* 6 ? ? 1.8 v low level reset detection time t llr ? 200 ? ? s cold0=0* 6 ? ? 1.1 release reset voltage v rer cold0=1* 6 ? ? 1.8 v 1 *1: when low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. * 2 : use 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =1pf). * 3 : use 4.096mhz crystal osc illator chc49sfw b (kyocera). * 4 : 1024 clock average. * 5 : recommended operating temperature (ta = -20 to +70 c, ta = -40 to +85 c for p version) * 6 : the cold0 bit is the code-option which is set up into the flash memory. powe r -on reset activation power rise time (t por ) reset_n reset pulse width (p rst ) p rst vil1 vil1 vdd 0.9xv dd 0.1xv dd t por t llr v rer (cold0=1) v llr (cold0=0) v rer (cold0=0) low level reset release reset voltage v llr (cold0=1) low level reset detection time(t llr ) vdd low level reset detection voltage
fedl610q419-05 ML610Q419/ML610Q419c 24/38 dc characteristics (2/5) (v dd = 1.1 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. min. min. unit measuring circuit cn4-0 = 00h 0.89 0.94 0.99 cn4-0 = 01h 0.91 0.96 1.01 cn4-0 = 02h 0.93 0.98 1.03 cn4-0 = 03h 0.95 1.00 1.05 cn4-0 = 04h 0.97 1.02 1.07 cn4-0 = 05h 0.99 1.04 1.09 cn4-0 = 06h 1.01 1.06 1.11 cn4-0 = 07h 1.03 1.08 1.13 cn4-0 = 08h 1.05 1.10 1.15 cn4-0 = 09h 1.07 1.12 1.17 cn4-0 = 0ah 1.09 1.14 1.19 cn4-0 = 0bh 1.11 1.16 1.21 cn4-0 = 0ch 1.13 1.18 1.23 cn4-0 = 0dh 1.15 1.20 1.25 cn4-0 = 0eh 1.17 1.22 1.27 v l1 voltage v l1 v dd = 3.0v, tj = 25 c cn4-0 = 0fh 1.19 1.24 1.29 v cn4-0 = 10h 1.21 1.26 1.31 cn4-0 = 11h 1.23 1.28 1.33 cn4-0 = 12h 1.25 1.30 1.35 cn4-0 = 13h 1.27 1.32 1.37 cn4-0 = 14h* 1 1.29 1.34 1.39 cn4-0 = 15h* 1 1.31 1.36 1.41 1 cn4-0 = 16h* 1 1.33 1.38 1.43 cn4-0 = 17h* 1 1.35 1.40 1.45 cn4-0 = 18h* 1 1.37 1.42 1.47 cn4-0 = 19h* 1 1.39 1.44 1.49 cn4-0 = 1ah* 1 1.41 1.46 1.51 cn4-0 = 1bh* 1 1.43 1.48 1.53 cn4-0 = 1ch* 1 1.45 1.50 1.55 cn4-0 = 1dh* 1 1.47 1.52 1.57 cn4-0 = 1eh* 1 1.49 1.54 1.59 cn4-0 = 1fh* 1 1.51 1.56 1.61 v l1 temperature deviation ? v l1 v dd = 3.0v D -1.5 D mv/ c v l1 voltage dependency ? v l1 v dd = 1.3 to 3.6v D 5 20 mv/v v l2 voltage v l2 1/2bias D v l1 1 D vdd = 3.0v, tj = 25 c, 1/3bias typ. 09 v l1 2 D v l3 voltage v l3 300k ? load (v l3 ? v ss ) 1/2bias typ. 09 v l1 2 D v 1/3bias typ. 09 v l1 3 D lcd bias voltage generation time t bias D D D 100 ms
fedl610q419-05 ML610Q419/ML610Q419c 25/38 dc characteristics (3/5) (v dd = 1.1 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ld2?0 = 0h 1.35 ld2?0 = 1h 1.4 ld2?0 = 2h 1.45 ld2?0 = 3h 1.5 ld2?0 = 4h 1.6 ld2?0 = 5h 1.7 ld2?0 = 6h 1.8 ld2?0 = 7h 1.9 ld2?0 = 8h 2.0 ld2?0 = 9h 2.1 ld2?0 = 0ah 2.2 ld2?0 = 0bh 2.3 ld2?0 = 0ch 2.4 ld2?0 = 0dh 2.5 ld2?0 = 0eh 2.7 bld threshold voltage v bld v dd = 1.35 to 3.6v ld2?0 = 0fh typ. ? 2% 2.9 typ. +2% v bld threshold voltage temperature deviation ? v bld v dd = 1.35 to 3.6v ? 0 ? %/ c ta = 25 c ? 0.4 0.8 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. * 6 ? ? 8 a ta = 25 c ? 0.9 1.8 supply current 2 idd2 cpu: in halt state (ltbc, rtc: operating* 3 * 5 ). high-speed oscillation: stopped. lcd/bias circuits: stopped. * 6 ? ? 9 a ta = 25 c ? 5 8 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 3 high-speed oscillation: stopped. lcd/bias circuits: operating.* 2 * 6 ? ? 15 a ta = 25 c ? 80 100 supply current 4 idd4 cpu: in 500khz cr operating state. lcd/bias circuits: operating.* 2 * 3 * 6 ? ? 120 a 1 ta = 25 c ? 0.9 1.0 supply current 5 idd5 cpu: in 4.096mhz operating state.* 2 * 3 pll: in oscillating state. lcd/bias circuits: operating. * 2 v dd = 1.8 to 3.6v * 6 ? ? 1.2 ma ta = 25 c ? 1.5 1.6 supply current 6 idd6 cpu: in 4.096mhz operating state.* 2 pll: in oscillating state. * 3 * 4 a/d: in operating state. lcd/bias circuits: operating. * 2 v dd = av dd = 3.0v * 6 ? ? 2.5 ma * 1 : cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock: 1/128 lsclk (256hz) * 3 : use 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =1pf). * 4 : use 4.096mhz crystal osc illator chc49sfw b (kyocera). * 5 : significant bits of blkcon0~blkcon4 registers are all ?1?. * 6 : recommended operating temperature (ta = -20 to +70 c, ta = -40 to +85 c for p version)
fedl610q419-05 ML610Q419/ML610Q419c 26/38 dc characteristics (4/5) (v dd = 1.1 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ? ? ioh1 = -0.1ma, v dd = 1.3 to 3.6v v dd ? 0.3 ? ? voh1 ioh1 = -0.03ma, vdd = 1.1 to 3.6v v dd ? 0.3 ? ? iol1 = +0.5ma, v dd = 1.8 to 3.6v ? ? 0.5 iol1 = +0.1ma, v dd = 1.3 to 3.6v ? ? 0.5 output voltage 1 (p20?p22/2 nd function is selected) (p30?p36) (p40?p47) (p50?p53) (p60?p67) *1 vol1 iol1 = +0.03ma, v dd = 1.1 to 3.6v ? ? 0.3 ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ? ? ioh1 = -0.1ma, v dd = 1.3 to 3.6v v dd ? 0.3 ? ? voh2 ioh1 = -0.03ma, v dd = 1.1 to 3.6v v dd ? 0.3 ? ? output voltage 2 (p20?p22/2 nd function is not selected) vol2 iol2 = +5ma, v dd = 1.8 to 3.6v ? ? 0.5 output voltage 3 (p40?p41) vol3 iol3 = +3ma, v dd = 2.0 to 3.6v (when i 2 c mode is selected) ? ? 0.4 voh4 ioh4 = ? 0.05ma, vl1=1.2v v l3 ? 0.2 ? ? voml4 iomh4 = +0.05ma, vl1=1.2v ? ? v l2 +0.2 voml4s iomh4s = ? 0.05ma, vl1=1.2v v l2 ? 0.2 ? ? volm4 ioml4 = +0.05ma, vl1=1.2v ? ? v l1 +0.2 volm4s ioml4s = ? 0.05ma, vl1=1.2v v l1 ? 0.2 ? ? output voltage 4 (com0?3) (seg0?39) (seg40?47) *2 vol4 iol4 = +0.05ma, vl1=1.2v ? ? 0.2 v 2 iooh voh = v dd (in high-impedance state) ? ? 1 output leakage (p20?p22) (p30?p35) (p40?p47) (p50?p53) (p60?p67) *1 iool vol = v ss (in high-impedance state) ? 1 ? ? a3 iih1 vih1 = v dd 0 ? 1 v dd = 1.8 to 3.6v ? 600 ? 300 ? 20 v dd = 1.3 to 3.6v ? 600 ? 300 -10 input current 1 (reset_n) (test1_n) iil1 vil1 = v ss v dd = 1.1 to 3.6v ? 600 ? 300 -2 v dd = 1.8 to 3.6v 20 300 300 300 ? ? v dd = 1.8 to 3.6v 2 30 200 v dd = 1.3 to 3.6v 0.2 30 200 iih2 vih2 = v dd (when pulled-down) v dd = 1.1 to 3.6v 0.01 30 200 v dd = 1.8 to 3.6v ? 200 ? 30 ? 2 v dd = 1.3 to 3.6v ? 200 ? 30 -0.2 iil2 vil2 = v ss (when pulled-up) v dd = 1.1 to 3.6v ? 200 ? 30 ? ? 1 input current 2 (p00?p03) (p10?p11) (p30?p35) (p40?p47) (p50?p53) (p60?p67) *1 iil2z vil2 = v ss (in high-impedance state) ? 1 ? ? a4 *1: ML610Q419c only *2: ML610Q419 only
fedl610q419-05 ML610Q419/ML610Q419c 27/38 dc characteristics (5/5) (v dd = 1.1 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit v dd = 1.3 to 3.6v 0.7 v dd ? v dd vih1 v dd = 1.1 to 3.6v 0.7 v dd ? v dd v dd = 1.3 to 3.6v 0 ? 0.3 v dd input voltage 1 (reset_n) (test1_n) (test0) (p00?p03) (p10?p11) (p31?p35) (p40?p43) (p45?p47) (p50?p53) (p60?p67) *1 vil1 v dd = 1.1 to 3.6v 0 ? 0.2 v dd vih2 ? 0.7 v dd ? v dd input voltage 2 (p30, p44) vil2 ? 0 ? 0.3 v dd v 5 input pin capacitance (p00?p03) (p10?p11) (p30?p35) (p40?p47) (p50?p53) (p60?p67) *1 cin f = 10khz v rms = 50mv ta = 25 c ? ? 5 pf ? *1: ML610Q419c only
fedl610q419-05 ML610Q419/ML610Q419c 28/38 measuring circuits measuring circuit 1 measuring circuit 2 v v dd v ddl v l1 v l2 v l3 v ss vil (*1) input logic circuit to determine the specified measuring conditions. (*2) measured at the specified output pins. (*2) (*1) vih av dd v ref av ss input pins output pins xt0 xt1 p10/osc0 p11/osc1 32.768khz crystal 4.096mhz crystal c gh c dh a v dd v ddl c l1 c l0 v l1 v l2 v l3 c a c b c c v ss c2 c1 c 12 c v c v : >2.2 f c l1 : 0.1 f c a ,c b ,c c : 0.1 f c 12 : 0.47 f c gl ,c dl : 1pf c gh ,c dh : 24pf 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) 4.096mhz crystal: hc49sfwb (kyocera) c gl c dl av dd v ref av ss
fedl610q419-05 ML610Q419/ML610Q419c 29/38 measuring circuit 3 measuring circuit 4 measuring circuit 5 vih vil (*1) *1: input logic circuit to determine the specified measuring conditions. v dd v ddl v l1 v l2 v l3 v ss av dd v ref av ss input pins output pins waveform monitoring a *3: measured at the specified output pins. (*3) v dd v ddl v l1 v l2 v l3 v ss av dd v ref av ss input pins output pins a vih vil *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) (*1) v dd v ddl v l1 v l2 v l3 v ss av dd v ref av ss input pins output pins
fedl610q419-05 ML610Q419/ML610Q419c 30/38 ac characteristics (external interrupt) (v dd = 1.1 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 ? 106.8 s ac characteristics (uart) (v dd = 1.3 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt ? ? brt* 1 ? s receive baud rate t rbrt ? brt* 1 ? 3% brt* 1 brt* 1 +3% s *1: baud rate period (including the error of the clock frequency selected) set with the uart baud rate register (ua0brtl,h) and the uart mode register 0 (ua0mod0). t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) p00?p03 (both-edge interrupt) t nul t nul t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt
fedl610q419-05 ML610Q419/ML610Q419c 31/38 ac characteristics (synchronous serial port) (v dd = 1.3 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit when high-speed oscillation is not active* 2 (v dd = 1.3 to 3.6v) 10 ? ? s sclkn input cycle (slave mode) t scyc when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) 1 ? ? s sclkn output cycle (master mode) t scyc ? ? sclkn* 1 ? s when high-speed oscillation is not active* 2 (v dd = 1.3 to 3.6v) 4 ? ? s sclkn input pulse width (slave mode) t sw when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) 0.4 ? ? s sclkn output pulse width (master mode) t sw ? sclkn* 1 0.4 sclkn* 1 0.5 sclkn* 1 0.6 s when high-speed oscillation is not active* 2 (v dd = 1.3 to 3.6v) ? ? 500 soutn output delay time (slave mode) t sd when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) ? ? 240 ns when high-speed oscillation is not active* 2 (v dd = 1.3 to 3.6v) ? ? 500 soutn output delay time (master mode) t sd when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) ? ? 240 ns sinn input setup time (slave mode) t ss ? 80 ? ? ns when high-speed oscillation is not active* 2 (v dd = 1.3 to 3.6v) 500 ? ? sinn input setup time (master mode) t ss when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) 240 ? ? ns when high-speed oscillation is not active* 2 (v dd = 1.3 to 3.6v) 300 ? ? sinn input hold time t sh when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) 80 ? ? ns n= 0,1 *1: clock period selected with snck3?0 of the serial port n mode register (sionmod1) * 2 : when rc oscillation is selected with oscm1?0 of the frequency control register (fcon0) * 3 : when crystal/ceramic oscillation, built-in pll oscillation, or external clock input is selected with oscm1?0 of the frequency control register (fcon0) t sd sclkn* sinn* soutn* *: indicates the secondar y function of the p ort. t sd t ss t sh t sw t sw t scyc
fedl610q419-05 ML610Q419/ML610Q419c 32/38 ac characteristics (i2c bus interf ace: standard mode 100khz) (v dd = 1.8 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 100 khz scl hold time (start/restart condition) t hd:sta ? 4.0 ? ? s scl ?l? level time t low ? 4.7 ? ? s scl ?h? level time t high ? 4.0 ? ? s scl setup time (restart condition) t su:sta ? 4.7 ? ? s sda hold time t hd:dat ? 0 ? 3.45 s sda setup time t su:dat ? 0.25 ? ? s sda setup time (stop condition) t su:sto ? 4.0 ? ? s bus-free time t buf ? 4.7 ? ? s ac characteristics (i 2 c bus interface: fast mode 400khz) (v dd = 1.8 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 400 khz scl hold time (start/restart condition) t hd:sta ? 0.6 ? ? s scl ?l? level time t low ? 1.3 ? ? s scl ?h? level time t high ? 0.6 ? ? s scl setup time (restart condition) t su:sta ? 0.6 ? ? s sda hold time t hd:dat ? 0 ? 0.9 s sda setup time t su:dat ? 0.1 ? ? s sda setup time (stop condition) t su:sto ? 0.6 ? ? s bus-free time t buf ? 1.3 ? ? s p41/scl p40/sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl610q419-05 ML610Q419/ML610Q419c 33/38 ac characteristics (rc oscillation a/d converter) condition for vdd=1.8 to 3.6v (v dd =1.8 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs0,rs1,rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 D D k ? f osc1 resistor for oscillation=1k ? 457.3 525.2 575.1 khz f osc2 resistor for oscillation=10k ? 53.48 58.18 62.43 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=100k ? 5.43 5.89 6.32 khz kf1 rt0, rt0-1, rt1=1k ? 7.972 9.028 9.782 ? kf2 rt0, rt0-1, rt1=10k ? 0.981 1 1.019 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt0, rt0-1, rt1=100k ? 0.099 0.101 0.104 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0-cs0 oscillation) f oscx (rt0-1-cs0 oscillation) f oscx (rt1-cs1 oscillation) kfx = f oscx (rs0-cs0 oscillation) , f oscx (rs0-cs0 oscillation) , f oscx (rs1-cs1 oscillation) ( x = 1, 2, 3 ) v dd v ddl c l v ss c v rt0, rt0-1, rt1: 1k /10k /100k rs0, rs1: 10k cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf rcm frequency measurement (f oscx ) input pin vih vil *1: input logic circuit to determine the specified measuring conditions. cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 rt1 in0 cvr0 cvr1 (note 1)
fedl610q419-05 ML610Q419/ML610Q419c 34/38 condition for vdd=1.25 to 3.6v (v dd =1.25 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs0,rs1,rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 D D k ? f osc1 resistor for oscillation=6k ? 81.93 93.16 101.2 khz f osc2 resistor for oscillation=15k ? 35.32 38.75 41.48 khz oscillation frequency v dd = 1.5v f osc3 resistor for oscillation=105k ? 5.22 5.65 6.03 khz kf1 rt0, rt0-1, rt1=1k ? 2.139 2.381 2.632 ? kf2 rt0, rt0-1, rt1=10k ? 0.973 1 1.028 ? rs to rt oscillation frequency ratio *1 v dd = 1.5v kf3 rt0, rt0-1, rt1=100k ? 0.142 0.147 0.152 ? f osc1 resistor for oscillation=6k ? 85.28 94.58 103.3 khz f osc2 resistor for oscillation=15k ? 35.72 38.87 41.78 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=105k ? 5.189 5.622 6.012 khz kf1 rt0, rt0-1, rt1=1k ? 2.227 2.432 2.626 ? kf2 rt0, rt0-1, rt1=10k ? 0.982 1 1.018 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt0, rt0-1, rt1=100k ? 0.141 0.145 0.149 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0-cs0 oscillation) f oscx (rt0-1-cs0 oscillation) f oscx (rt1-cs1 oscillation) kfx = f oscx (rs0-cs0 oscillation) , f oscx (rs0-cs0 oscillation) , f oscx (rs1-cs1 oscillation) ( x = 1, 2, 3 ) note: - please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistor s and in0/in1 pin), including cvr0/cvr1. especially, do not have long wire between in0/in1 and rs0/rs1. the coupling capacitance on the wires may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. - when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have vss(gnd) trace next to the signal. - please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. rt0, rt0-1, rt1: 1k /10k /100k ra0, ra0-1, ra1: 5k rs0, rs1: 15k cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf frequency measurement (f oscx ) input pin *1: input logic circuit to determine the spec ifi ed m easu rin g co n d i t i o n s . (note 1) v dd v ddl c l v ss c v rcm vih vil cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 in0 cvr0 cvr1 ra1 ra0-1 rt1 ra0
fedl610q419-05 ML610Q419/ML610Q419c 35/38 electrical characteristics of successi ve approximation type a/d converter (v dd = 1.8 to 3.6v, av dd =2.2 to 3.6v, v ss = av ss = 0v, ta = -20 to +70 c, ta = -40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resolution n ? ? ? 12 bit 2.7v v ref 3.6v ? 4 ? +4 integral non-linearity error idl 2.2v v ref 2.7v ? 6 ? +6 2.7v v ref 3.6v ? 3 ? +3 differential non-linearity error dnl 2.2v v ref 2.7v ? 5 ? +5 zero-scale error v off ? ? 6 ? +6 full-scale error fse ? ? 6 ? +6 lsb reference voltage v ref ? 2.2 ? av dd v sack = 0 (hsclk = 375khz to 625khz) ? 25 ? conversion time t conv sack = 1 (hsclk = 1.5mhz to 4.2mhz) ? 112 ? /ch : period of high-speed clock (hsclk) a v dd av dd v ref v ddl v ddx v ss av ss analog input 1 ? ri ?
fedl610q419-05 ML610Q419/ML610Q419c 36/38 package dimensions (unit: mm) notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl610q419-05 ML610Q419/ML610Q419c 37/38 revision history page document no. date previous edition current edition description fedl610q419-1 dec.26.2011 ? ? formally edition 1.0 fedl610q419-2 jan.11.2012 35 35 changed figure of package dimensions. fedl610q419-3 jun.5.2012 3 3 changed part number of tqfp. fedl610q419-4 sep.4.2012 21 21 changed parameter of data retention. changed parameter of 1-word (16 bits) write time all all change header and footer 3 4 change from "shipment" to " product name ? supported function " - 22 add clock generation circuit operating conditions 22 23 change "reset" to "reset pulse width (p rst )" , " power-on reset activation power rise time (t por )" and ?low level reset detection time(t llr )?. 22 23 correct the cgl?s value and the cdl?s value of dc characteristics (1/5)?s note no.2 24 25 correct the c gl ?s value and the c dl ?s value of dc characteristics (3/5)?s note no.3 fedl610q419-05 july.25.2014 27 28 correct the c gl ?s value and the c dl ?s value of measuring circuit 1
fedl610q419-05 ML610Q419/ML610Q419c 38/38 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011-2014 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

▲Up To Search▲

Price & Availability of ML610Q419

	To Download ML610Q419 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .